In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical design. EE V: VLSI Physical Design Automation (Spring ). Prof. David Z. Pan. Lecture hours and location: MW am at SZB Instructor contact. VLSI Physical Design Automation: Theory and Practice [Sadiq M Sait] on *FREE* shipping on qualifying offers. Vlsi is an important area of.


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Algorithms for VLSI Physical Design Automation

Abstract In Optimization of VLSI Physical Design, area minimization and interconnect length minimization is an important objective in physical vlsi physical design automation automation of very large scale integration chips.

The objective of minimizing the area and interconnect length would scale down the size of integrated chips. To meet the above objective, it is necessary to find an optimal solution for physical design components vlsi physical design automation partitioning, floorplanning, placement, and routing.

This work helps to perform the optimization of the benchmark circuits with the above said components of physical design using hierarchical approach of evolutionary algorithms. The goal of minimizing the delay in partitioning, minimizing the silicon area in floorplanning, minimizing the layout area in placement, minimizing the wirelength in routing has indefinite influence on other criteria like power, clock, speed, cost, and so forth.


Hybrid evolutionary algorithm is applied on each of its phases to achieve the objective. Because evolutionary algorithm that includes vlsi physical design automation or many local search steps within its evolutionary cycles to obtain the minimization of area and interconnect length.

This approach combines a hierarchical design like genetic algorithm and simulated annealing to attain the objective. This hybrid approach can quickly produce optimal solutions for the popular benchmarks.

Introduction Physical design automation has been an active area of research for atleast three decades.

Algorithms for VLSI Physical Design Automation

The main reason is that physical design of chips has become a crucial and critical design task today due to the enormous increase of system complexity and the future advances of electronic circuit design and fabrication.

Most commonly used high-level synthesis tools allow the designers to automatically generate huge systems simply by just changing a few lines of code in vlsi physical design automation functional specification. Nowadays, the open source codes simulated in open source software can automatically be converted to hardware description codes, but the automatically generated codes are not optimized ones.

Synthesis and simulation tools often cannot hold with the complexity of the entire system under development. Every time designers want to concentrate vlsi physical design automation typical parts of a system to upgrade the speed of the design cycle.

Mathematical Problems in Engineering

Thus the present vlsi physical design automation design technology requires a better solution for the system with fast and effective optimization [ 1 ]. Moreover, fabrication and packing technology makes the demand for increasing smaller feature sizes and augmenting the die dimensions possible to allow a circuit for accommodating several millions of transistors; however, logical circuits are restricted in their size and in the number of external pin connections.

So the technology requires partitioning vlsi physical design automation a system into manageable components by arranging the circuit blocks without wasting empty spaces.

The direct implementation of large circuit without going for optimization will occupy large area. Hence the large circuit is necessary to split into small subcircuits. This will minimize the area of the manageable system and the complexity of the large system.

Optimal Solution for VLSI Physical Design Automation Using Hybrid Genetic Algorithm

When the circuit is partitioned, the connection between two modules or say partitions should be minimum. It is a design vlsi physical design automation by applying a hierarchical algorithmic approach to solve typical combinatorial optimization problems like dividing a large circuit system into smaller pieces.

Figure 1 shows the design flow for the proposed approach.

Design flow for the proposed approach. The method of finding block positions and shapes with minimizing the area objective is referred to as floorplanning. The input to the floorplanning is the output of system partitioning and design entry.